This invention concerns a process and a circuit layout for using an independent capacitor for the momentary retention of an output voltage when an input voltage is lost.
This type of independent capacitor circuitry is already familiar from DE 195 42 085 A1. The interfacing circuitry of DC/DC converters facilitates increased capacitor voltage compared to the input and output voltage which facilitates a reduction in capacitance at a constant amount of charge. A circuit layout of this type is shown in FIG. 2. The input voltage (Ue) is transformed by a DC/DC up converter (1) to a higher capacitor voltage (Uc) which is fed to the independent capacitor (C). The voltage level is stabilised and is largely independent from the input voltage (Ue). Capacitor voltage (Uc) is transformed by a DC/DC down converter (2) to the given level of output voltage (Ua) and fed to the load element (L). The discharge curve of the independent capacitor (Uc) in FIG. 4 clearly shows the disadvantage of this layout, as the independent time interval (T.sub.autark) only lasts until the output voltage (Ua) is reached. The residual voltage remaining in the independent capacitor (C) cannot be used, as the DC/DC down converter (2) can no longer utilise it.